Multiprocessor system having switches for routing cells in parallel among processors by splitting data into blocks having numbers of cells equals to proccessor bus width

摘要

In a multiprocessor system including a plurality of processors and asynchronous transfer mode (ATM) switches in the number corresponding to a bit width of internal buses of respective processors each processor has an interface for connecting in parallel to each of the plurality of ATM switches. Each interface splits a transmission data block into a plurality of bit data blocks at every bit position, converts them into a plurality of cells by adding a header including routing information determined by a destination processor to each bit data block, and sends these cells in parallel to the plurality of ATM switches. The plurality of cells are transferred in parallel to the destination processors by the ATM switches and reassembled into an original data block in the interface of the destination processor.