发明名称 Memory cache with automatic alliased entry invalidation and method of operation
摘要 A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and waits until the data is requested again before it invalidates any cache aliased entries in the semi-associative cache array. This invalidation step requires no dedicated cycle but instead is a result of the memory cache being able to simultaneously read from the semi-associative cache array and the cache reload buffer.
申请公布号 US5550995(A) 申请公布日期 1996.08.27
申请号 US19940176812 申请日期 1994.01.03
申请人 MOTOROLA, INC.;INTERNATIONAL BUSINESS MACHINES 发明人 BARRERA, DAVID D.;RASTEGAR, BAHADOR;ROSSBACH, PAUL C.
分类号 G06F12/08;G06F12/10;(IPC1-7):G06F12/12 主分类号 G06F12/08
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