发明名称 Apparatus and method for residual error clock skew bound, and clocking therewith
摘要 Multiple clocks are interconnected in a network which is fed and controlled by a clock generator. A delay of one or more clock periods less a fixed amount is imposed between any two such clocks excluding the clock generator, to cause the repeated clock so transferred to occur at the appropriate time in the next cycle. Feedback using such delays assures bounded phase differences among these clocks. Thus, skew bounds can be provided for large numbers of clocks, to provide a bounded delay among multiple clocks. There is inserted in each link between a pair of clock nodes a delay line that delays a propogating clock signal by just enough time to cause the repeated clock to occur at the appropriate time in the next cycle, thereby synchronizing the appearance of that clock signal at the various nodes. Self-oscillation of the system, if the clock generator is removed, is avoided by having the delay between any two directly connected nodes be greater than one period of that clock generator.
申请公布号 US5550875(A) 申请公布日期 1996.08.27
申请号 US19940366201 申请日期 1994.12.29
申请人 UNISYS CORPORATION 发明人 BENNETT, DONALD B.
分类号 G06F1/10;H04J3/06;(IPC1-7):H04L7/00 主分类号 G06F1/10
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