发明名称 |
Secondary clock source for low power, fast response clocking |
摘要 |
An integrated digital logic circuit includes a free-running secondary clock oscillator for generating free-running clocking pulses and a frequency-stabilized master oscillator for generating primary clocking pulses. A clock signal selector selects and puts out either the secondary clocking pulses or the primary clocking pulses depending upon integrated circuit operations/applications. A method for rapidly generating clocking signals during an integrated circuit start-up interval is also described.
|
申请公布号 |
US5550489(A) |
申请公布日期 |
1996.08.27 |
申请号 |
US19950536314 |
申请日期 |
1995.09.29 |
申请人 |
QUANTUM CORPORATION |
发明人 |
RAAB, MICHAEL L. |
分类号 |
G06F1/08;G06F1/32;(IPC1-7):H03K19/096 |
主分类号 |
G06F1/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|