| 摘要 |
<p>A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1 and din2, and generates, in response to a first control signal Ζ1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal Ζ2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal Ζ0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, Ζ1 and Ζ2, is such that the second control signal Ζ2 is activated LOW after a finite period following the initial activation of the first control signal Ζ1. The third control signal Ζ0 is preferably activated LOW when the first and second control signals, Ζ1 and Ζ2, are inactive HIGH.</p> |
