| 摘要 |
A communications receiver such as an integrated zero IF receiver comprises an input for receiving an input signal and a zero IF frequency down conversion means (12 to 24) coupled said input and constructed to provide quadrature related signals (I, Q) at a substantially zero intermediate frequency. In order to balance the signal paths, at least one capacitance (C-Fig. 3 not shown) in each of the quadrature related zero IF signal paths of the frequency down conversion means comprises at least two integrated capacitors (c1, c2-Fig. 4 not shown) connected in anti-parallel. By fabricating the integrated capacitances in this way the symmetry of the circuit is maintained which enhances significantly the second-order inter-modulation performance.
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