发明名称 |
Integrierte Halbleiterschaltung mit Prüfschaltung |
摘要 |
A semiconductor integrated circuit includes a plurality of data buses (DB1-DB4), and emitter-follower circuits (Q11-Q81, Q12-Q82) arranged in the data buses. Read parts (SA1-SA4), which are coupled to the emitter-follower circuits, read data transferred via the data buses via the emitter-follower circuits. A test part (TC, TC0-TC4), which is coupled to the data buses via the emitter-follower circuits, determines, in a test mode, whether or not the data transferred via the data buses have an error and outputs a test output signal to at least one (DB4) of the data buses. The output test signal has a potential level higher than that of the data transferred via the data buses in a normal mode. <IMAGE> |
申请公布号 |
DE69120921(D1) |
申请公布日期 |
1996.08.22 |
申请号 |
DE1991620921 |
申请日期 |
1991.12.20 |
申请人 |
FUJITSU LTD., KAWASAKI, KANAGAWA, JP |
发明人 |
OKAJIMA, YOSHINORI, C/O FUJITSU LIMITED, KAWASAKI-SHI, KANAGAWA 211, JP |
分类号 |
G01R31/28;G11C29/00;G11C29/12;G11C29/34;G11C29/36;H01L21/66;(IPC1-7):G06F11/26 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|