发明名称 |
CACHE MEMORY ACCESS TIME CONTROL CIRCUIT |
摘要 |
a latch clock generator generating a latch clock signal in a central processing unit(CPU); a delay means which delays the latch clock signal, being connected between the latch clock output terminal and the latch clock input terminal of the CPU; and a flip flop means latching the data read from a cache memory with the delayed signal as a clock signal.
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申请公布号 |
KR960011280(B1) |
申请公布日期 |
1996.08.21 |
申请号 |
KR19930017548 |
申请日期 |
1993.08.31 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, JOON;HONG, BUM - YONG;HWANG, SEUNG - HOE |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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