| 摘要 |
A high-performance "low-RC" multi-level interconnect technology has been conceived for advanced sub-0.5 mu m semiconductor technologies. The proposed structure and fabrication process has a number of significant characteristics: (i) compatible with various metal systems (Al, Cu, W, etc.), (ii) free-space interlevel dielectrics; (iii) compatible with standard semiconductor fabrication processes, (iv) excellent mechanical stability; and (v) compatible with hermetically sealed chip packaging techniques. Compared with an Al-based conventional interconnect technology, the new interconnect system can reduce the "RC" delay by a factor of -6. The proposed interconnect technology offers major chip performance improvements such as lower power dissipation and higher operating frequencies. This technology is based on a manufacturable process to fabricate multilevel interconnect with free-space dielectrics and a technology scaling enabler.
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