| 摘要 |
PROBLEM TO BE SOLVED: To realize a sealed package having minimum size and weight and being drastically reduced of power loss. SOLUTION: Laminated chip layers 10 are provided and each of the chip layers is provided with multiple via holes 40, 42 and 44 piercing through the chip layer from the top surface to the bottom surface of the chip layer. The via holes of each are connected to pads 41a, 41b, 43a, 43b, 45a and 45b formed on the top surface and the bottom surface of the chip layers. The patterns of traces 24, 26, 30 and 32 are formed on one side surface of a board and connected to the via hole pads according to the design. An integrated circuit of which pads 14 are connected to some of the traces with wires is mounted on the other side of the board. The chip layers are arranged so that the via holes of each layer match those of the other layer and the via hole pads on the top and the bottom surfaces of each layer. |
