| 摘要 |
PURPOSE: To improve such a situation that, when shift registers are connected in a multistage cascade manner, the speed of a clock cannot be made faster when a serial data output from a previous-state shift register to be input to a next-stage shift register to which a common clock signal is input, is delayed due to the delay of an inverter for buffer. CONSTITUTION: Up to the (n-1)st stage of (n) bits of shift registers which shift data at the rise of a clock signal CLK are constituted of ordinary D-type flip- flops 2, and the n-th stage is constituted of a master slave D-type flip-flop 3. Then, at a serial data output terminal QN, a master output MQ from the flip-flop 3 is taken out via a two-stage inverter 1. The master output MQ is output at the rise of an n-th clock signal CLK, it is made faster as compared with a conventional case in which a data output Qn from the last-stage D-type flip-flop used in the serial data output terminal QM is output at the fall of the n-th clock signal, and the delay of the inverter 1 is compensated. |
