发明名称 DECODER AND MPEG VIDEO DECODER
摘要 <p>PURPOSE: To obtain an MPEG video decoder at a low cost. CONSTITUTION: When a switching circuit 5 is switched to the side of a node 5a and a switching circuit 6 is switched to the side of a node 6b, a video output is stored in an area 4a of a display buffer 4. After storing a video output for sixteen lines in the area 4a, the circuit 5 is switched to the side of a node 5b and the circuit 6 is switched to the side of a node 6a. Thereby a video output is stored in an area 4b of the buffer 4. The video output for sixteen lines stored in the area 4a is outputted to a display as a high resolution still picture output through the node 6a of the circuit 6. Said operation is repeated in each video output of sixteen lines. Since one macro block in an MPEG video part is constituted of sixteen lines, a video output for sixteen lines is outputted to the display.</p>
申请公布号 JPH08214300(A) 申请公布日期 1996.08.20
申请号 JP19950029833 申请日期 1995.02.17
申请人 SANYO ELECTRIC CO LTD 发明人 OKADA SHIGEYUKI
分类号 H04N5/91;G06T9/00;H03M7/30;H04N5/92;H04N19/00;H04N19/423;H04N19/426;(IPC1-7):H04N7/24 主分类号 H04N5/91
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