DELAY LINE OF IMAGE SENSOR

摘要

The delay line comprises a transfer part including multiple transfer devices for transferring signals with a first CCD input terminal for a first PL broadcasting mode and a second CCD input for an NTSC broadcasting mode. Multiple clocking gates are provided for selecting the first or second input terminals and a control circuit is provided for controlling the gates in order to select a specific broadcasting mode signal. The CCD input terminals are integrated within a single chip. The control circuit includes transfer gates for passing or blocking clock signals in accordance with a level of a control and applies the clocks to the inputs.