A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.
申请公布号
US5548786(A)
申请公布日期
1996.08.20
申请号
US19940224123
申请日期
1994.04.06
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
AMINI, NADER;BOURY, BECHARA F.;BRANNON, SHERWOOD;CONCILIO, IAN A.;HOFMANN, RICHARD G.;LOHMAN, TERENCE J.