High-frequency clock generator using lower frequency voltage controlled ring oscillator

摘要

A low noise high-frequency clock generator using a low speed voltage controlled oscillator which includes 2m differential delay elements connected in series in an inverting configuration, where m is an integer greater than 0. The output of the 2mth delay element is coupled to the input of the first delay element in a non-inverting configuration. M 2-input exclusive NOR gates are provided wherein respective input pairs are taken from positive terminal inputs of adjacent delay elements. The clock generator also includes an m-input OR gate coupled to the m-outputs from the respective m exclusive NOR gates for generating the clock generator output signal. The delay elements have a variable delay associated therewith controlled by a control delay signal DCS. Changes in the delay associated with each delay element changes the frequency of the clock generator output signal wherein the output frequency is equal to 1/(2d), where d is the time delay associated with each delay element.