发明名称 BUS CONTROL SYSTEM
摘要 A bus control system for controlling intermultiprocessor communication by polling, comprising a listener response signal line for transferring an end answer signal from a listener circuit to a talker circuit immediately when the transfer of data between the talker and the listener is finished, without waiting for the completion of data transfer within the receiving processor, whereby the bus occupation period is shortened.
申请公布号 CA2036066(C) 申请公布日期 1996.08.20
申请号 CA19912036066 申请日期 1991.02.11
申请人 FUJITSU LIMITED 发明人 TAHIRA, FUMIAKI;SUMITANI, KAZUO;FUJISONO, KENJI;KAWASAKI, KEIKO;IGI, YOSO
分类号 G06F13/36;G06F13/366;(IPC1-7):G06F13/36 主分类号 G06F13/36
代理机构 代理人
主权项
地址