发明名称 METHOD FOR CREATION OF MULTILEVEL METALLIZED LAYER IN INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To manufacture a multilevel integrated circuit independent of a specific metallized wire and an open area pattern of a chip, by using a mask wherein the part correspondent to the metal layer of a grid pattern is eliminated, for depositing dummy features in an open area between metal lines. SOLUTION: Dummy features having the same width and distance as metal lines 14, 16 are formed in an open area 18, and an upper side dialectic layer 20 is made a plane. Mask structure 24 which is used for deposition and manufacture of the dummy features is provided with an opaque grid pattern 26 on a transparent base 28. CAD data of the pattern of each metallized layer are adopted to be superposed on the pattern of a metal line 30 while keeping an adequate distance on the grid pattern 26. At the position of a superposed master metal line, a part of the grid pattern 26 is eliminated. The adopted pattern for forming a specific pattern consists of the opaque metallized line pattern 30 and the residual opaque grid pattern 26.
申请公布号 JPH08213396(A) 申请公布日期 1996.08.20
申请号 JP19950287752 申请日期 1995.11.07
申请人 AT & T CORP 发明人 KUOOFUA RII;CHIYUNNTEIN RIU;RIICHIEN RIU
分类号 H01L21/3205;H01L21/768;H01L23/52;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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