| 摘要 |
<p>PURPOSE: To obtain an EEPROM whose write time does not become longer even when the frequency of an oscillator drops due to a low voltage by providing the EEPROM with an oscillation circuit which supplies a clock to a timing generation circuit generating two or more kinds of erase/write timings according to an output signal from a power-supply voltage level detection circuit. CONSTITUTION: A power-supply voltage level detection circuit 11 outputs a signal CTL according to a power-supply voltage VCC. A timer 12, to which the signal CTL and an output OSC from an oscillation circuit 10 are input, frequency-divides the OSC so as to generate the write time IWT according to the CLT. Thereby, even when the frequency of the circuit 10 drops due to the change in power-supply voltage VCC, it is possible to prevent the write time IWT from becoming longer than required.</p> |
