| 摘要 |
PURPOSE: To surely prevent a through current by providing two clocked CMOS inverter circuits with two clocks in which there is no period when pulses are at high levels in the same cycle simultaneously respectively. CONSTITUTION: An output state of fist-state/feedback clocked CMOS inverter circuits 2, 5 is controlled respectively by clocksϕ1, inverse ofϕ1,ϕ2, inverse ofϕ2. The clocksϕ1,ϕ2 are biphase clocks in which pulses are not simultaneously at an H for the same cycle. The circuit 2 is made up of P-MOS 2a, 2b and N-MOS 2c, 2d and the circuit 5 is made up of P-MOS 5a, 5b and N-MOS 5c, 5d. Through the constitution above, there is no period when a clock gate of the circuit 2 and a clock gate of the circuit 5 are not simultaneously conductive and then a through current is surely prevented.
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