Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions

摘要

A method for manufacturing a CMOS transistor of integrated circuits having metal gates and self-aligned source and drain electrodes. The channel length can be precisely defined, and the leakage current can be reduced. Furthermore, the threshold voltage of the transistor can be increased by implanting impurities into the well or the substrate.