发明名称 DECODER, MPEG AUDIO DECODER, MPEG VIDO DECODER AND MPEG SYSTEM DECODER
摘要 PURPOSE: To obtain an MPEG decoder, which can sufficiently obtain the synchronization of an audio output and a video output. CONSTITUTION: In each of decoders 2 and 3, the reproducing time of each output (audio output and video output) is set based on the decode processing time and SCR and PTS (PTS (A) of audio and PTS (V) of vido) in each decoder 2. The PTS, which is read out of each of registers 11 and 21, is transferred into each of control circuits 14 and 24. The bit stream, which is read out of each of bit buffers 12 and 22, is transferred into each of decode core circuits 13 and 23. In each of the control circuits 14 and 24, the reproducing time of each output is computed based on the decode processing time in each of the decoders 2 and 3 and SCR and PTS. In each of the decode core circuits 12 and 23, each output is formed based on the specifications of MPEG. The reproducing time of each output is controlled based on the result of the computation of each of the control circuits 14 and 24.
申请公布号 JPH08212701(A) 申请公布日期 1996.08.20
申请号 JP19940317114 申请日期 1994.12.20
申请人 SANYO ELECTRIC CO LTD 发明人 OKADA SHIGEYUKI;YAMAUCHI HIDEKI
分类号 H04N5/93;G11B20/10;H04L7/00;H04N7/52 主分类号 H04N5/93
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