| 摘要 |
<p>PURPOSE: To provide the bit phase synchronizing circuit where the number of phase timings of a read memory prescribing signal is increased and a small number of memories are provided. CONSTITUTION: A write control means WK1 generates the write memory prescribing signal, which cyclically varies memories MEM1 and MEM2 where respective bit values of input data are stored, based on a first clock C1 and gives this signal to a memory part M1, and respective bit values are cyclically stored in memories. A read control means RK1 generates a read memory prescribing signal, which cyclically varies memories from which stored values are outputted, based on a second clock C2 having n-fold ((n) is an integer equal to or larger than 2) frequency of the first clock, and gives this signal to the memory part, and stored bit values are successively outputted from memories. The read control means RK1 can generate plural kinds of read memory prescribing signals, and a phase comparison meansϕCOMP makes the read control means RK1 output the read memory prescribing signal of the different phase at the time of contention between write to and read from the same memory.</p> |
