| 摘要 |
<p>A circuit for generating test-mode signals for memory which uses both hardware and software protection schemes. The circuit enters a test code by receiving a high voltage at two terminals. The high voltage must remain on at least one of the terminals during the test code process. Otherwise, the circuit is reset. The test code contains test code bits and format code bits. The format code bits are the same for all test codes and distinguish the test codes from commands.</p> |
