COHERENT SAMPLING DIGITIZER SYSTEM

摘要

A digitizing system coherently samples an input signal (12) of frequency Ft and generates an output data sequence representing magnitudes of N successive samples. The digitizing system generates a timing signal by frequency dividing (16) a clock signal of frequency FMCLK by an integer factor K and supplies the timing signal to a digitizer (14). The digitizer (14) coherently samples the input signal N times over M cycles of the input signal to produce an N-term data sequence representing one cycle of the input signal. The timing signal frequency sets the digitizer sampling rate. The digitizing system includes a computer (22) programmed to execute an algorithm for finding an appropriate value of K so that the system substantially achieves coherent sampling of the input signal despite limitations in allowable ranges of K, M and N. The algorithm searches a Farey series to locate terms of the form P/Q from which it may derive candidate values of K (K = Qi*J), M (M = P*J) and N (N = Qi), wherein P and Q are relatively prime integers, J is integer greater than 0 and Qi is an integer factor of Q. The algorithm locates the particular Farey series term most closely approximating the ratio Ft/FMCLK for which candidate values of K, M and N fall within their allowable ranges. The digitizing system then frequency divides the master clock signal by that candidate value of K.