Personalized area leadframe coining or half etching for reduced mechanical stress at device edge
摘要
A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.
申请公布号
US5545921(A)
申请公布日期
1996.08.13
申请号
US19940334478
申请日期
1994.11.04
申请人
INTERNATIONAL BUSINESS MACHINES, CORPORATION;SIEMENS AKTIENGESELLSCHAFT
发明人
CONRU, HAROLD W.;FROEBEL, FRANCIS E.;GREGORITSCH, JR., ALBERT J.;RIELEY, SHELDON C.;STARR, STEPHEN G.;UTTECHT, RONALD R.;WHITE, ERIC J.;POHL, JENS G.