| 摘要 |
A rotating priority selection circuit executes a priority scheme for the purpose of selecting which of several possible instructions that should be executed next in a microprocessor design that allows for the execution of out of sequence instructions. The priority logic circuit selects instructions for execution based executing the oldest, by age, pending instruction if it is ready (i.e., operands available), but if the oldest instruction is not ready, then executing the next to oldest if it is ready and so on. The topology used borrows from a concept used for fast parallel adders. Logic at each node in the circuit produces the equivalent of a carry generate and a carry propagate. "Carries" are routed around the loop to cause input responses which are lower in priority to be suppressed. This loop is broken, so as not to feed back on itself, at the node which is pointed to by the pointer bus. The number of gate delays in this network is half that of prior schemes.
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