| 摘要 |
A method of enabling a controllable and variable number of bits to be written to a group of cells of a DRAM or SRAM simultaneously in a block, wherein a predecoded column address signal is decoded for enabling writing to cells of the DRAM or SRAM, and the predecoded column address signal is block overwritten by means of a block address signal, whereby plural decoders are enabled simultaneously for simultaneous writing to a column of cells notwithstanding the logic levels of the predecoded address signal.
|
