| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern preparation method for reducing a pattern amount giving delay inserted at the time of test patter preparation for input terminal skew verification. SOLUTION: In a circuit in which input terminals 1, 2, 3, 4 are connected to the input pin 11 of an order circuit 10, and input pins 12, 13, 14 by an combination circuit 16, cases in which attributions are accorded are made a group, pattern insertion is not performed between grouped terminals and an inserted pattern amount is suppressed when the pattern insertion for verifying the presence of malfunction of an output value by skew with a tester is made in the input terminal in a case where an input terminal 5 connected to the lock input pin 15 of the order circuit 10 and the input terminals 1, 2, 3, 4 are changed simultaneously. |
