| 摘要 |
<p>PURPOSE: To provide the method inexpensively without employment of a high speed component and of an analog circuit such as a PLL. CONSTITUTION: The device realizing the method is provided with means 18, 19 generating two phase signals whose phase is deviated from a reference clock with a frequency almost twice the transmission frequency of a transmission signal. Three criteria of phase lead, phase lag and in-phase are provided based on combinations of the two phases and at which point of time of the three criteria a change point of data with a definite length takes place is monitored. Then the phase of the clock signal is corrected or not corrected based on it that to which of the three criteria a change point of the data of the definite length corresponds, only a change in bit middle point of data after correction or original definite length data is extracted and a change in the bit midpoint to be extracted is used for timing information.</p> |
