| 摘要 |
PURPOSE: To allow the PLL circuit to surely follow a large phase change by providing a sufficient capture range even if the digital filter has an arithmetic processing delay. CONSTITUTION: A signal level converter 46 is provided to an output stage in a digital filter 40 and when either a high level or a low level of a control signal Y2(t) outputted from an adder 44 reaches a maximum value Vmax or a minimum value GND, the low level or high level of the control signal Y2(t) is converted into the minimum value GND or the maximum value Vmax at the signal level converter 46 respectively. After the signal Y2'(t) after the conversion is converted into an analog voltage at a D/A converter 5, the converted signal is fed to a VCXO6 as a control signal voltage Vout. |
