发明名称 PHASE REGULATION CIRCUIT
摘要 PURPOSE: To regulate a phase to be a desired one by obtaining a comparison result signal between a reference signal and a DC level and varying its edge timing by varying the DC level. CONSTITUTION: A reproduction signal RF from a magnetic head 2 is converted into serial data D1 and their inverted data D1I via an amplified 3 and a binarizing circuit 4, a PLL circuit 5 obtains a phase comparison result with a reference signal and the reference signal is controlled to generate a recovery clock CK. The clock CK is converted into a since signal by a band pass filter 7, the waveform is shaped so that the rising and the trailing parts of the signal are smoothly changed and a comparison result signal S2 with respect to a reference voltage VR varied with a variable resistor 10 is obtained in a buffer amplified 9. The signal S2 is given to a waveform shaping circuit 11, from which a recovery clock S3 and its inverted signal S3I are recovered. Thus, the resistor 10 is operated to vary a phase continuously and thereby regulating the phase to be a desired one easily.
申请公布号 JPH08204546(A) 申请公布日期 1996.08.09
申请号 JP19950030237 申请日期 1995.01.27
申请人 SONY CORP 发明人 YAMASHITA SHIGEYUKI
分类号 G11B20/14;H03L7/00 主分类号 G11B20/14
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