发明名称 Microcomputer chip layout
摘要 <p>A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor. &lt;IMAGE&gt;</p>
申请公布号 EP0725349(A2) 申请公布日期 1996.08.07
申请号 EP19950112432 申请日期 1995.08.08
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 SHIMIZU, TORU;SAWAI, KATSUNORI;SHIMAZU, YUKIHIKO;KUMANOYA, MASAKI;DOSAKA, KATSUMI
分类号 G06F13/16;G06F13/00;G06F15/78;(IPC1-7):G06F13/16 主分类号 G06F13/16
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