| 摘要 |
<p>A programmable logic circuit (202 - 204) that accepts three input signals (A, B, C) from a logic gate array of logic devices on a programmable logic device and to produce a selected logic function as output signal (219) that depends on the input signals, the circuit comprises logic expander means having first, second and third data input terminals (199-1, 199-2, 199-3) for receiving three input signals A, B and C, respectively, having an output terminal, and having up to eight control input terminals (CB0 - CB7) to receive control signals thereat, for producing a desired output signal (OUT) that is selectively determined by the control signals and is equivalent to the logical sum of logic variables CS0 . A . B . C + CS1 . A* . B . C + CS2 . A . B* . C + CS3 . A . B . C* + CS4 . A* . B* . C + CS5 . A* . B . C* + CS6 . A . B* . C* + CS7 . A* . B* . C*, where CS0, CS1, CS2, CS3, CS4, CS5, CS6 and CS7 are control signals delivered to the control input terminals; and programming means for providing the control signals at the control input terminals to produce a desired output signal for the logic expander means. <IMAGE></p> |
