发明名称 SYSTEM AND METHOD FOR TESTING A PROGRAMMABLE LOGIC
摘要 The present invention provides a system and method for self-testing and self-checking programmable logic. According to the preferred embodiment, a system is provided which includes a multiplexer having an output coupled to the input of programmable logic, and inputs coupled to normal input signal sources and a pseudo-random number generator. The multiplexer selectively couples an input to its output responsive to an input source signal. The output of the programmable logic is applied to normal output components and a data compression register which is controlled by a read enable signal. The system further includes a configuration control which independently generates the input select signal and the read enable signal.
申请公布号 EP0584917(A3) 申请公布日期 1996.08.07
申请号 EP19930305406 申请日期 1993.07.09
申请人 ADVANCED MICRO DEVICES, INC. 发明人 PEDNEAU, MICHAEL D.
分类号 G01R31/28;G01R31/3183;G01R31/3185;G06F11/27;H03K19/00;H03K19/173;(IPC1-7):G06F11/26 主分类号 G01R31/28
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