Fine resolution digital delay line with coarse and fine adjustment stages
摘要
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.
申请公布号
US5544203(A)
申请公布日期
1996.08.06
申请号
US19940324856
申请日期
1994.10.18
申请人
TEXAS INSTRUMENTS INCORPORATED
发明人
CASASANTA, JOSEPH A.;ANDRESEN, BERNHARD H.;SATOH, YOSHINORI;KEENEY, STANLEY C.;MARTIN, ROBERT C.