发明名称 |
Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module |
摘要 |
A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three dimensional interconnect network from a two dimensional arrangement of arrays or chips in a MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed. |
申请公布号 |
US5543640(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19950536076 |
申请日期 |
1995.09.29 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
SUTHERLAND, JAMES;GARVERICK, TIMOTHY L.;TAKIAR, HEM P.;REYLING, JR., GEORGE F. |
分类号 |
H01L23/538;H01L25/065;H01L27/02;H03K19/177;(IPC1-7):H01L27/10 |
主分类号 |
H01L23/538 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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