发明名称 |
Process for forming an electrically programmable read-only memory cell |
摘要 |
A floating gate (51) is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
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申请公布号 |
US5543339(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19940296908 |
申请日期 |
1994.08.29 |
申请人 |
MOTOROLA, INC. |
发明人 |
ROTH, SCOTT S.;KIRSCH, HOWARD C. |
分类号 |
H01L21/8247;H01L29/423;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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