发明名称 Gate array architecture and layout for deep space applications
摘要 The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy, and charged particles. In one embodiment of the present invention, the gate array comprises a first and a second logical component, and a first and a second isolation transistor. Both first and second isolation transistors comprise an input, a biasing bus having a voltage potential, and an electrical contact for electrically coupling the biasing bus with the input. Moreover, the gate array comprises a redundant coupling for increasing the immunity of the gate array to charged particles, electromagnetic radiation and photon energy.
申请公布号 US5543736(A) 申请公布日期 1996.08.06
申请号 US19930165236 申请日期 1993.12.10
申请人 UNITED TECHNOLOGIES CORPORATION 发明人 GARDNER, HARRY N.;GREGORY, CHARLES R.;GARVIE, DOUGLAS W.
分类号 H01L27/118;(IPC1-7):H01L25/00;H03K19/00 主分类号 H01L27/118
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