发明名称 |
Method for manufacturing offset polysilicon thin-film transistor |
摘要 |
In a method for fabricating an offset polysilicon thin-film transistor through the formation of silicide, the width of offset regions can be controlled as a narrow width of below 1 mu m. Drain voltage is decreased due to the reduction of the offset regions' width. The effect of an increased parallel resistance and a bias voltage dependency of an overlap capacitance due to the arrangement of low concentration ion region reduces leakage current and improves the response to applied voltages. Also, gate voltage is decreased due to the decreased gate resistance when the polysilicon of the gate is substituted with the silicide.
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申请公布号 |
US5543340(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19940363201 |
申请日期 |
1994.12.27 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, JOO-HYUNG |
分类号 |
H01L21/28;H01L21/3205;H01L21/335;H01L21/336;H01L23/52;H01L29/49;H01L29/78;H01L29/786;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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