发明名称 |
Semiconductor integrated circuit having logic gates |
摘要 |
An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
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申请公布号 |
US5544125(A) |
申请公布日期 |
1996.08.06 |
申请号 |
US19950383866 |
申请日期 |
1995.02.06 |
申请人 |
HITACHI, LTD. |
发明人 |
YOKOYAMA, YUJI;AKIOKA, TAKASHI;IWAMURA, MASAHIRO;HIRAISHI, ATSUSHI;KOBAYASHI, YUTAKA;YAMAUCHI, TATSUMI;TAKAHASHI, SHIGERU;GOTOU, NOBUYUKI;IDE, AKIRA |
分类号 |
G11C7/10;G11C8/10;H03K19/0948;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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