Radar decoder

摘要

A radar decoder circuit for converting NRZL Data to radar video data which is supplied to a radar video display screen. The radar video circuit includes an Erasable Programmable Logic Device which decodes incoming NRZL data to identify a frame sync having twenty four data bits. When the frame sync is identified the location of sixteen bits of synchro data is also determined. The synchro data is then latched into a latch within the Erasable Programmable Logic Device for processing by a Digital-to-Synchro Converter. Control signals for effecting a transfer of the synchro data to the Digital-to-Synchro Converter are provided by enable and latch signal generating circuit within the Erasable Programmable Logic Device. The Digital-to-Synchro Converter converts the digital synchro data to analog synchro signals which are supplied to the radar video display allowing the display to indicate the direction the radar from which the NRZL data is received is pointing. The Erasable Programmable Logic Device also includes a marker generating circuit which generates a ten kilometer marker pulse signal and a fifty kilometer marker pulse signal for use by the radar video display as well as trigger pulse signal which is used as timing reference indicator by the radar video display.