| 摘要 |
logic sections (20-23) for compensating for the phase variation of a motion vector according to the 4-phase configuration of memories; adders (24-28) for adding a macro slice address (MSA) to a motion vector Y (MVY), and a macro block address (MBA) to a motion vector X (MVX) respectively; the first latches (29-33) for synchronizing the read addressing data of frame memories (49-56); the second latches (16)(17) for synchronizing the write addressing data of the frame memories (49-56); clock counters (18)(19)(34-38) for counting clocks; multiplexers (39-48) for changing the read/write addressing data of the frame memories (49-56); decoders (59)(60) for determining the order of four phases of the memory data; an adder (61) for summing the IDCT and the motion-compensated data; a control section (62) for controlling the decoders (59)(60); multiplexers (63)(64); and a memory (68), and a first-in first-out memory(68). |
