发明名称 |
Dual gate fet and process |
摘要 |
The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.
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申请公布号 |
US2001001486(A1) |
申请公布日期 |
2001.05.24 |
申请号 |
US20010757153 |
申请日期 |
2001.01.09 |
申请人 |
HSU LOUIS LU-CHEN;WANG LI-KONG |
发明人 |
HSU LOUIS LU-CHEN;WANG LI-KONG |
分类号 |
H01L21/336;H01L29/786;(IPC1-7):H01L29/76;H01L31/062;H01L29/94;H01L31/113 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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