Verbesserung eines Verfahrens zum Planarisieren einer integrierten Schaltungsanordnung unter Verwendung eines anorganischen Materials mit niedrigem Schmelzpunkt

摘要

A planarizing process for planarizing an integrated circuit structure (14) in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises depositing a low melting inorganic planarizing layer (34) such as a boron oxide glass over a layer of insulating material (20) such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer (40) of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus. In a particularly preferred embodiment, all of the steps are carried out in the same chamber of the apparatus. An additional etching step may be carried out after depositing the first insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.