Fault tolerant computer architecture

摘要

The architecture has two redundant processing chains (C1, C2), each ensuring the same operating function, and a monitoring unit (3), which has a processor ensuring the operation monitoring of the two processing chains (C1, C2). Each chain (C1, C2) includes an acquisition circuit (4, 6), a transmission circuits (5, 7) and a processor (1, 2) ensuring the operation monitoring of the other chain. Each chain (C1, C2) and the monitoring unit (3) delivers data (Fij, i and j varying from 1 to 3) respectively relative to the operating state of the chains (C1, C2) and of the monitoring unit (3). The computer also includes a polling unit (11) connected to the two chains (C1, C2) and to the monitoring unit (3) so as to receive the data (Fij) to determine if one of the two chains (C1, C2) or the monitoring unit (3) is fault, and selection device (12) only transmits the results (S1, S2) provided by the two chains when they are functioning correctly.