| 摘要 |
A decoder circuit comprises a shift register 30 and a decoder 40, 50. The shift register 30 is coupled to receive a data bit stream 20. The decoder 40, 50 contains a set of unique codes, and is coupled to the shift register 30 for identifying when a pattern within the shift register 30 matches one of the set of unique codes within the decoder 40, 50 , and for providing a decoded output in dependence upon the matched one of the set of unique codes. The shift register 30 is initially set with a predetermined bit pattern which is arranged such that when a last bit of a valid variable length word enters the shift register 30 , the combination of the valid word and a residual portion of the predetermined bit pattern defines a pattern equal to one of the set of unique codes. |
