发明名称 |
A method and system for reducing dispatch latency in a processor |
摘要 |
<p>A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache. <IMAGE></p> |
申请公布号 |
EP0724213(A2) |
申请公布日期 |
1996.07.31 |
申请号 |
EP19950480192 |
申请日期 |
1995.12.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ELLIOT, TIMOTHY ALAN;OLSON, CHRISTOPHER HANS;MUHICH, JOHN STEPHEN;POTTER, TERENCE MATTHEW |
分类号 |
G06F9/38;G06F12/08;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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