Method and apparatus for improving performance of out of sequence load operations in a computer system

摘要

The invention provides for improved performance of out of sequence load operations. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its instruction set, and an address compare unit (ACU). During compilation, the improved compiler identifies load operations that can be move out of sequence ahead of associated store operations and moves those load operations out of sequence and flags them as such. The associated store operations are also flagged. During processor execution of a compiled and optimized program, the address of operands fetched by the out of sequence load operations are saved to the new associative memory. On request, the ACU compares the addresses saved to the addresses generated by the associated store operations. If a comparison results in an identity between the address of a store operation and an address of the out of sequence load operation, a recovery code is run to correct the problem, if not the system continues to execute the program in its compiled order. The system also has the ability to work in a multiprogramming or multitasking environment.