Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities

摘要

An address of any desired instruction in a super-scalar processor is generated using address tracking logic. A sequential address register in the last stage of the processor's pipelines holds the address of the last or oldest instruction in the pipelines. This register is updated with a target address when a branch instruction is actually taken. A pipeline valid array contains valid bits for the instructions in the pipelines, and also contains the lengths of the instructions for complex instruction sets having instructions that vary in length. The address of the desired instruction is calculated as the sum of a base address and an adjustment value. The base address is the address of the last instruction which is stored in the sequential address register when there are no intervening taken branches between the desired instruction and the last instruction in the pipelines. When there is an intervening taken branch, the target address from the taken branch closest to the desired instruction is selected as the base address. The adjustment value is the sum of all the instruction lengths for instructions between the desired instruction and the last instruction, or the closest intervening taken branch if it exists. A branch resolver uses this address tracking logic to generate the address of a branch instruction being resolved, and the address of the following sequential instruction. A recovery address for branch mis-prediction sent to the instruction fetcher is the following sequential address when the branch is actually not taken, and is the target address when the branch is actually taken. The branch can be resolved in any pipeline stage.