发明名称 |
Output circuit for an TTL-CMOS integrated circuit |
摘要 |
An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.
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申请公布号 |
US5541533(A) |
申请公布日期 |
1996.07.30 |
申请号 |
US19950432926 |
申请日期 |
1995.05.01 |
申请人 |
MATRA MHS |
发明人 |
MARTINEZ, RAYMOND;BION, THIERRY |
分类号 |
H03K19/003;H03K19/017;H03K19/0185;(IPC1-7):H03K19/017 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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